Enhanced EUV Lithography System

ABSTRACT

The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.

PRIORITY DATA

The present application is a continuation application of U.S. patentapplication Ser. No. 14/807,999, filed on Jul. 24, 2015, now U.S. Pat.No. ______ issued ______, which is a continuation application of U.S.patent application Ser. No. 13/437,145, filed on Apr. 2, 2012, now U.S.Pat. No. 9,091,930 issued Jul. 28, 2015, the disclosure of which ishereby incorporated by reference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs and, forthese advances to be realized, similar developments in IC processing andmanufacturing are needed. In the course of IC evolution, functionaldensity (i.e., the number of interconnected devices per chip area) hasgenerally increased while geometry size (i.e., the smallest apparatusthat can be created using a fabrication process) has decreased.

To achieve the shrinking geometry sizes, advanced lithography processeshave been developed. For example, the use of extreme ultraviolet (EUV)lithography has been proposed to achieve small geometry sizes. Due toheavy absorption of EUV radiation by substances, an EUV lithographysystem typically uses a reflective optics apparatus to carry out thelithography processes. However, conventional EUV lithography systems maysuffer from a shadow effect, which may lead to device pattern uniformityissues or otherwise degrade lithography performance.

Therefore, while existing EUV lithography apparatuses and processes havebeen generally adequate for their intended purposes, they are notentirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a simplified block diagram of an extreme ultraviolet (EUV)lithography system according to various aspects of the presentdisclosure.

FIG. 2 is a simplified cross-sectional view of an EUV photo maskaccording to various aspects of the present disclosure.

FIG. 3A is a simplified perspective view of a pattern on an EUV photomask according to various aspects of the present disclosure.

FIG. 3B is a simplified top view of a portion of an EUV photo mask witha plurality of patterns according to various aspects of the presentdisclosure.

FIG. 4 is a simplified top view of a portion of an EUV photo mask withsome of the patterns shown in greater detail according to variousaspects of the present disclosure.

FIG. 5 is a flowchart illustrating a method of fabricating asemiconductor device according to various aspects of the presentdisclosure.

FIG. 6 is a computer system for performing some of the processesdiscussed above with reference to FIGS. 1-5 according to various aspectsof the present disclosure.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of variousembodiments. Specific examples of systems and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

The use of extreme ultraviolet (EUV) lithography has been proposed toachieve increasingly small semiconductor device geometry sizes. Anexample EUV lithography system 100 is illustrated in FIG. 1. The EUVlithography system 100 includes a light source apparatus 110. The lightsource apparatus 110 is operable to generate radiation beams having avery small wavelength, for example a wavelength smaller than about 50nanometers (nm), and even as small as about 10-15 nm in some cases. Incertain embodiments, the light source apparatus 110 produces the smallwavelength radiation beams in a laser-produced plasma (LPP) system,which uses a high power laser to create a high energy plasma that canemit the radiation beams having the small wavelengths. This can be doneinside a vacuum chamber. In other embodiments, a discharge-producedplasma (DPP) method can be used to generate the radiation beams. Due atleast in part to such small wavelengths, the EUV system 100 can achieveenhanced resolution for the semiconductor features to be patterned.

The EUV lithography system 100 includes illumination optics apparatus120. The illumination optics apparatus 120 may include a collectoroptics apparatus to collect the radiation beams produced by the lightsource apparatus 110. The illumination optics apparatus 120 alsoincludes a plurality of mirrors. These mirrors are operable to reflectthe radiation a number of times. Since the radiation beams are highlyabsorbable due to the small wavelength, the material compositions of themirrors are carefully configured to minimize radiation absorption. Insome embodiments, to reduce absorption of the radiation beams, aplurality of alternating Molybdenum (Mo) and Silicon (Si) layers areused are a part of the mirrors. In some cases, specializedanti-absorption coating may also be applied to these mirrors to furtherreduce radiation absorption. And since gas such as air or nitrogen mayalso absorb the radiation beams, the entire illumination optics may beimplemented inside a vacuum chamber in some embodiments. It isunderstood that additional contamination control measures may beimplemented inside the illumination optics apparatus 120 to reduce thepossibility of contamination.

The EUV lithography system 100 includes a mask apparatus 130. The maskapparatus 130 may include a multi-layered mask. The multi-layered maskmay include a material having a low thermal expansion coefficient as anunderlying substrate. A reflective multi-layer coating may be formedover substrate. The multi-layer coating may include a number ofalternating material layers. The material layers may exhibit differingEUV reflectivity constants. For example, the multi-layer coating caninclude forty pairs of alternating Mo-Si layers. An absorber layer suchas a TaN material layer may be disposed over the reflective multi-layercoating. A buffer layer such as a silicon dioxide layer may be disposedbetween the reflective multi-layer coating and the absorber layer toprotect the multi-layer coating during the mask patterning process. Adesired pattern for the EUV mask is defined by selectively removingportions of the absorber layer and the buffer layer to uncover portionsof the underlying multi-layer coating on the substrate, therebyproviding a patterned EUV mask. The absorber layer may be selectivelyremoved by a combination of patterning (e.g., laser-beam and/orelectron-beam writing) and etching (e.g., wet and/or dry etching)processes.

The EUV lithography system 100 includes a projection optics apparatus140. The radiation beams are sent to the mask apparatus 130 from theillumination optics apparatus 120, and then propagated to the projectionoptics apparatus 140. The projection optics apparatus 140 may includeone or more reflective mirrors, lenses, condensers, etc. The projectionoptics apparatus 140 may utilize ring field optics instruments. In thepresent embodiments, the projection optics apparatus 140 includes anaperture (or a slit) that is shaped like a portion of a ring, or an arc.In various embodiments, the mask apparatus 130 is positioned over theprojection optics apparatus 140.

The EUV lithography system 100 includes a wafer stage apparatus 150. Thewafer stage apparatus 150 is operable to hold a wafer that is to bepatterned. The wafer stage apparatus 150 is positioned underneath theprojection optics apparatus 140. In some embodiments, the wafer stageapparatus 150 includes an electronic chuck (E-chuck), which uses anelectronic force to secure a wafer. In other embodiments, the waferstage apparatus 150 includes a chuck that uses clamps to secure a wafer.The wafer stage apparatus 150 is movable to allow various regions of thewafer to be stepped and scanned.

Referring now to FIG. 2, a simplified diagrammatic fragmentarycross-sectional side view of an EUV lithography photo mask 200 is shown.The photo mask 200 may be implemented as an embodiment of themulti-layered mask for the mask apparatus 130 of FIG. 1. The photo mask200 includes a silicon substrate 210. A plurality of silicon layers 220and molybdenum layers 230 are located over the silicon substrate 210 inan alternating or interleaving manner. That is, a molybdenum layer 230is located on a silicon layer 220, and another silicon layer 220 islocated on the molybdenum layer 230, so on and so forth. A ruthenium(Ru) layer 240 is located on the alternating silicon-molybdenum layers.

The photo mask 200 also includes a plurality of layout patterns 250.These patterns 250 may represent semiconductor device features to bepatterned on a semiconductor wafer, for example gate lines for MetalOxide Semiconductor (MOS) transistors. In the illustrated embodiment,the patterns 250 each include a tantalum boron nitride (TaBN) component260 and a lawrencium component 270. It is understood that the variousmaterials and layers disclosed herein for the photo mask 200 are merelyexamples and are not intended to be limiting. Other materials and layerconfigurations may be employed for alternative photo masks 200. Inaddition, it is understood that the various layers are not drawn toscale in FIG. 2. For example, the alternating silicon and molybdenumlayers 220-230 may have varying thicknesses.

A light 280 (for example, the EUV radiation beam generated by the lightsource apparatus 110) in an EUV lithography system is projected towardthe photo mask 200 at a non-incident angle. That is, the light 280 isprojected toward the photo mask 200 in a tilted manner and thus forms anincident angle 290 with a vertical axis 300 that is perpendicular to thesurface of the photo mask 200. In some embodiments, the incident angle290 is in a range from about 5 degrees to about 7 degrees. The reflectedlight 310 is then projected toward the projection optics (not shown inFIG. 2) to carry out the EUV lithography process. However, since thepatterns 250 have a height, the tilted light 280 (or the reflected light310) will cause shadows 320 to be present on the surface of the photomask 200. This is referred to as a shadow effect or a shadow bias, whichmay degrade lithography performance and is therefore undesirable.

In the following paragraphs, methods and systems to substantiallyeliminate the shadow effect will be discussed. According to variousaspects of the present disclosure, the layout patterns on an EUV photomask will be rotated (or arranged) so that they are aligned according totheir respective azimuthal angles. In more detail, refer now to FIGS.3A-3B, where FIG. 3A is a simplified perspective view of an examplepattern 250A on an EUV photo mask, and FIG. 3B is a simplified top viewof a portion of an EUV photo mask 200A on which a plurality of patterns250A are located.

Three axes X, Y, Z are shown in FIGS. 3A and 3B. These three axes X, Y,and Z are orthogonal to one another. The X and Y axes collectivelydefine a horizontal plane, for example a plane of the surface of thephoto mask 200A on which the EUV light is projected. In someembodiments, the Y axis is the scan axis, and the X axis is the slitaxis. The slit axis mostly defines the direction of the slit or apertureof the projection optics. An example slit or aperture 350 of the EUVprojection optics is shown in FIG. 3B. As is illustrated, the slit 350has a shape of an arc (or a portion of a ring) in the presentembodiment. It is understood that the slit 350 is not an actual featureformed on the photo mask 200A. FIG. 3B merely shows what a superpositionof the slit 350 and the photo mask 200A would look like. The Z axisdefines a vertical direction and represents the vertical axis 300 ofFIG. 2. It is against the Z axis that the incident angle 290A is formedby the EUV light 280A. The projection of the light 280A onto thehorizontal plane defined by the X and Y axes forms an azimuthal angle360 with the Y axis.

The slit 350 is also correlated with the azimuthal angle 360. Dependingon the location of a point on the slit 350, the azimuthal angle would bedifferent. For example, in some embodiments, the end points of the slit350 (end points of the arc) have corresponding angles of about 66degrees and 114 degrees, respectively. That is, assuming the center ofthe slit is defined a 90 degrees, then the end points varies by −24 and24 degrees, respectively, thereby arriving at 66 (66=90-24) degrees and114 (114=90+24) degrees.

According to various aspects of the present disclosure, each pattern250A points in a direction that is perpendicular to the arc of the slit350. That is, each pattern 250A is substantially aligned with itscorresponding azimuthal angle. Thus, the orientations of the patterns250A are functions of their locations on the photo mask 200A. Forexample, as shown in FIG. 3B, the patterns 250A whose locationscorrespond to the center of the slit have azimuthal angles that aresubstantially equal to about 90 degrees. The patterns 250A whoselocations correspond to the left of the center of the slit haveazimuthal angles that are less than 90 degrees, for example about 66degrees if the pattern's location corresponds to the left edge of theslit 350. The patterns 250A whose locations correspond to the right ofthe center of the slit have azimuthal angles that are greater than 90degrees, for example about 114 degrees if the pattern's locationcorresponds to the right edge of the slit 350.

To illustrate the above concept in more detail, refer to FIG. 4, whichis a simplified diagrammatic top view of a portion of the photo mask200A. The slit 350 is also shown in FIG. 4 as being superimposed overthe photo mask 200A. Three example patterns are illustrated as patterns380, 381, and 382. Similar to the patterns 250 shown in FIGS. 2-3, thepatterns 380-382 are elongate patterns and may be used to patternsemiconductor features such as gate lines on a wafer. The pattern 380 islocated in a position that corresponds to the center of the slit 350,and therefore its associated azimuthal angle is 90 degrees. The pattern380 is substantially aligned with the Y axis. The pattern 380 is shapedsubstantially as a rectangle.

The pattern 381 is located in a position that corresponds to a left ofthe center of the slit 350 (and thus to the left of the pattern 381).The pattern 381 is shaped substantially as a parallelogram. In otherwords, the pattern 381 has long sides 390 that are substantiallyparallel to each other, as well as short sides 391 that aresubstantially parallel to each other. The long side 390 forms an angle400 with the Y axis. The azimuthal angle associated with the pattern 381is (90-angle 400) degrees. For example, if the angle 400 is about 24degrees, then the azimuthal angle associated with the pattern 381 is 66degrees.

The pattern 382 is located in a position that corresponds to a right ofthe center of the slit 350 (and thus to the right of the pattern 380).The pattern 382 is shaped substantially as a parallelogram. In otherwords, the pattern 382 has long sides 410 that are substantiallyparallel to each other, as well as short sides 411 that aresubstantially parallel to each other. The long side 410 forms an angle420 with the Y axis. The azimuthal angle associated with the pattern 382is (90+angle 420) degrees. For example, if the angle 420 is about 24degrees, then the azimuthal angle associated with the pattern 382 is 114degrees.

Thus, it may be said that each of the patterns 380-382 is orientedaccording to its respective azimuthal angle. In other words, the longside (e.g., side 390 or 410) of each pattern 380-382 is substantiallyaligned with its azimuthal angle. Also, in an original design layout,the designer is constrained to design all the patterns to be orientedalong the Y axis (e.g., such as the pattern 380). According to thevarious aspects of the present disclosure, such original design layoutis transformed into the layout shown in FIG. 4, where the patterns notlocated at the center of the slit 350 are effectively “rotated” suchthat they are oriented according to their azimuthal angle. Theparallelogram shape of the non-slit-center patterns 381 and 382 are alsoobtained as a result of the pattern transformation. Theparallelogram-shaped patterns 381 and 382 have the same dimension 430 inthe Y-direction as that of their original rectangular patterns in thedesign layout, but their dimension 440 in the X-direction is greaterthan that of their original rectangular patterns in the design layout.For example, if the pattern 381′s original dimension in the X-directionis a dimension 450 (which is also the X-directional dimension of thepattern 380), then after the transformation, the new dimension in theX-direction for the pattern 381 is equal to: the dimension 450+thedimension 430*tan(φ), where φ is the azimuthal angle associated with thepattern 381. The new X-directional dimension for the pattern 382 can becalculated in a similar manner.

The shadow bias (due to the shadow effect) can be mathematicallyexpressed with the following equation:

Shadow bias˜=2*M*tan(θ)*sin²(φ+α−C)

where M is a magnification factor (magnification from photo mask towafer), θ is an incident angle, φ is an azimuthal angle, α is a variable(where α is θ for a vertical pattern oriented along the Y-axis, andwhere α is 90 for a horizontal pattern oriented along the X-axis), and Cis a variable that represents the orientation of the pattern. Thus, tominimize the shadow bias, the above equation should be manipulated sothat it yields zero. Specifically, the term sin²(φ+α−C) should be set to0. Since the design rules specify that all the patterns should be laidout in the vertical direction (aligned with the Y-direction) originally,α=0. Thus, C should be set to always be equal to the azimuthal angle φfor each pattern in order for the shadow bias to be substantiallyeliminated. Stated differently, the pattern after the transformationshould be oriented in the same direction as the azimuthal angleassociated with the pattern.

As discussed above, the patterns on the EUV photo mask can betransferred to a wafer. Thus, in some embodiments, the semiconductorfeatures formed on the in the wafer may also have polygonal shapes suchas the parallelograms illustrated in FIG. 4. Since the shadow bias issubstantially eliminated, the resolution of the semiconductor featuresformed on the wafer can be significantly improved. In variousembodiments, the semiconductor devices to be patterned on a wafer mayinclude, but are not limited to, memory circuits, logic circuits, highfrequency circuits, image sensors, and various passive and activecomponents such as resistors, capacitors, and inductors, P-channel fieldeffect transistors (pFET), N-channel FET (nFET), metal-oxidesemiconductor field effect transistors (MOSFET), or complementarymetal-oxide semiconductor (CMOS) transistors, bipolar junctiontransistors (BJT), laterally diffused MOS (LDMOS) transistors, highpower MOS transistors, or other types of transistors.

FIG. 5 is a flowchart of a method 600. The method 600 includes a block610, in which a design layout for a semiconductor device is received.The design layout contains a plurality of semiconductor patterns eachoriented in a given direction. In some embodiments, the design layout isreceived from a designer or a customer of a foundry. In certainembodiments, the given direction spans along a Y-axis, and wherein theY-axis defines a scan axis for a lithography process. The directionalconstraint placed on the entity providing the design layout may comefrom a foundry. The patterns may define semiconductor features to beformed on a wafer. For example, the patterns may each define a gateline. The method 600 includes a block 620, in which the design layout istransformed into a mask layout. The semiconductor patterns in the masklayout are oriented in a plurality of different directions as a functionof their respective location. In some embodiments, the semiconductorpatterns in the mask layout are each oriented in accordance with theirrespective azimuthal angle. In some embodiments, at least a subset ofthe semiconductor patterns are each shaped as a parallelogram. Themethod 600 includes a block 630, in which an extreme ultraviolet (EUV)lithography photo mask is manufactured based on the mask layout. In someembodiments, the foundry receives the design layout from its customer,and after transforming the design layout into a mask layout,manufactures an EUV photo mask based on the mask layout. In someembodiments, the foundry may outsource the actual manufacturing of theEUV photo mask to another vendor. The method 600 includes a block 640,in which a semiconductor wafer is fabricated using the EUV lithographyphoto mask. It should be noted that additional processes may be providedbefore, during, and after the method blocks shown in FIG. 5, and thatsome other processes may only be briefly described herein.

FIG. 6 is a block diagram of a computer system 800 suitable forimplementing various methods and devices described herein, for example,the various method blocks of the methods 400, 500, and 600 discussedabove. For example, the computer system 800 is operable to transform thedesign layout into the mask layout. In various implementations, thedevices of the computer system 800 may comprise a network communicationsdevice or a network computing device (e.g., mobile cellular phone,laptop, personal computer, network server etc.) capable of communicatingwith a network (e.g., an intranet or the Internet). It should beappreciated that each of the devices may be implemented as the computersystem 800 for communication with the network in a manner as follows.

In accordance with various embodiments of the present disclosure, thecomputer system 800, such as a local computer or a networked computersystem, includes a bus component 802 or other communication mechanismsfor communicating information, which interconnects subsystems andcomponents, such as processing component 804 (e.g., processor,micro-controller, digital signal processor (DSP), etc.), system memorycomponent 806 (e.g., RAM), static storage component 808 (e.g., ROM),disk drive component 810 (e.g., magnetic or optical), network interfacecomponent 812 (e.g., modem or Ethernet card), display component 814(e.g., cathode ray tube (CRT) or liquid crystal display (LCD)), inputcomponent 816 (e.g., keyboard), cursor control component 818 (e.g.,mouse or trackball), and image capture component 820 (e.g., analog ordigital camera). In one implementation, disk drive component 810 maycomprise a database having one or more disk drive components.

In accordance with embodiments of the present disclosure, computersystem 800 performs specific operations by processor 804 executing oneor more sequences of one or more instructions contained in system memorycomponent 806. Such instructions may be read into system memorycomponent 806 from another computer readable medium, such as staticstorage component 808 or disk drive component 810. In other embodiments,hard-wired circuitry may be used in place of (or in combination with)software instructions to implement the present disclosure.

Logic may be encoded in a computer readable medium, which may refer toany medium that participates in providing instructions to processor 804for execution. Such a medium may take many forms, including but notlimited to, non-volatile media and volatile media. In one embodiment,the computer readable medium is non-transitory. In variousimplementations, non-volatile media includes optical or magnetic disks,such as disk drive component 810, and volatile media includes dynamicmemory, such as system memory component 806. In one aspect, data andinformation related to execution instructions may be transmitted tocomputer system 800 via a transmission media, such as in the form ofacoustic or light waves, including those generated during radio wave andinfrared data communications. In various implementations, transmissionmedia may include coaxial cables, copper wire, and fiber optics,including wires that comprise bus 802.

Some common forms of computer readable media includes, for example,floppy disk, flexible disk, hard disk, magnetic tape, any other magneticmedium, CD-ROM, any other optical medium, punch cards, paper tape, anyother physical medium with patterns of holes, RAM, PROM, EPROM,FLASH-EPROM, any other memory chip or cartridge, carrier wave, or anyother medium from which a computer is adapted to read.

In various embodiments of the present disclosure, execution ofinstruction sequences to practice the present disclosure may beperformed by computer system 800. In various other embodiments of thepresent disclosure, a plurality of computer systems 800 coupled bycommunication link 830 (e.g., a communications network, such as a LAN,WLAN, PTSN, and/or various other wired or wireless networks, includingtelecommunications, mobile, and cellular phone networks) may performinstruction sequences to practice the present disclosure in coordinationwith one another.

Computer system 800 may transmit and receive messages, data, informationand instructions, including one or more programs (i.e., applicationcode) through communication link 830 and communication interface 812.Received program code may be executed by processor 804 as receivedand/or stored in disk drive component 810 or some other non-volatilestorage component for execution.

Where applicable, various embodiments provided by the present disclosuremay be implemented using hardware, software, or combinations of hardwareand software. Also, where applicable, the various hardware componentsand/or software components set forth herein may be combined intocomposite components comprising software, hardware, and/or both withoutdeparting from the spirit of the present disclosure. Where applicable,the various hardware components and/or software components set forthherein may be separated into sub-components comprising software,hardware, or both without departing from the scope of the presentdisclosure. In addition, where applicable, it is contemplated thatsoftware components may be implemented as hardware components andvice-versa.

Software, in accordance with the present disclosure, such as computerprogram code and/or data, may be stored on one or more computer readablemediums. It is also contemplated that software identified herein may beimplemented using one or more general purpose or specific purposecomputers and/or computer systems, networked and/or otherwise. Whereapplicable, the ordering of various steps described herein may bechanged, combined into composite steps, and/or separated into sub-stepsto provide features described herein.

The embodiments disclosed herein offer advantages over existinglithography processes. It is understood, however, that other embodimentsmay offer additional advantages, and that no particular advantage isrequired for all embodiments, and some advantages may only be brieflydiscussed herein. One advantage is that the shadow bias or shadow effectassociated with existing EUV lithography processes can be substantiallyeliminated. In various embodiments, the elimination of the shadow effectis achieved through orienting the patterns on a photo mask such thatthey are aligned as a function of their respective azimuthal angles.Another advantage is that the customer of a foundry need not make manyadjustments to its own design layout. The only design rule that thecustomer needs to follow is that the device patterns in the designlayout need to be oriented in the same direction, for example aY-direction (scan axis) direction. The pattern orientationtransformation can be performed by the foundry without the involvementor supervision of the customer (designer), thereby lessening the burdenfor the designer.

One of the broader forms of the present disclosure involves asemiconductor fabrication apparatus. The semiconductor fabricationapparatus includes: a lithography mask having a plurality of patterns,wherein at least two of the plurality of patterns are oriented indifferent directions, and wherein orientations of the at least twopatterns are a function of their locations over the mask.

In some embodiments, the mask is an extreme ultraviolet (EUV)lithography mask.

In some embodiments, the mask includes a plurality of alternatingSilicon-Molybdenum layers.

In some embodiments, the orientation of each pattern is substantiallyaligned with its corresponding azimuthal angle.

In some embodiments, at least a subset of the patterns are shapedsubstantially as parallelograms.

In some embodiments, each pattern defines a gate line for asemiconductor transistor.

In some embodiments, the semiconductor fabrication apparatus furtherincludes: a projection optics tool that is operable to transfer thepatterns of the mask onto a semiconductor wafer, wherein the projectionoptics tool contains a ring-like slit from which light passes through.

Another of the broader forms of the present disclosure involves asemiconductor lithography system. The semiconductor lithography systemincludes: a projection optics component, wherein the projection opticscomponent includes a curved aperture; and a photo mask positioned overthe projection optics component, wherein the photo mask contains aplurality of elongate semiconductor patterns, wherein the semiconductorpatterns each point in a direction substantially perpendicular to thecurved aperture of the projection optics component.

In some embodiments, the semiconductor lithography system is an extremeultraviolet (EUV) lithography system; and the photo mask includesmultiple reflective layers.

In some embodiments, the semiconductor patterns each have an associatedazimuthal angle based on their respective locations relative to thecurved aperture; and the semiconductor patterns are each shaped as afunction of their respective azimuthal angle.

In some embodiments, the semiconductor patterns are each orientedaccording to their respective azimuthal angles.

In some embodiments, at least some of the semiconductor patterns arepolygons containing no right angles.

In some embodiments, the aperture is shaped as an arc from a top view.

In some embodiments, at least a subset of the semiconductor patternseach define a gate line for a semiconductor transistor device.

Still another of the broader forms of the present disclosure involves amethod. The method includes: receiving a design layout for asemiconductor device, wherein the design layout contains a plurality ofsemiconductor patterns each oriented in a given direction; andtransforming the design layout into a mask layout, wherein thesemiconductor patterns in the mask layout are oriented in a plurality ofdifferent directions as a function of their respective location.

In some embodiments, the semiconductor patterns in the mask layout areeach oriented in accordance with their respective azimuthal angle.

In some embodiments, at least a subset of the semiconductor patterns inthe mask layout are each shaped as a parallelogram.

In some embodiments, the given direction spans along a Y-axis, andwherein the Y-axis defines a scan axis for a lithography process.

In some embodiments, the method further includes manufacturing anextreme ultraviolet (EUV) lithography photo mask based on the masklayout.

In some embodiments, the method further includes fabricating asemiconductor wafer using the (EUV) lithography photo mask.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor fabrication apparatus,comprising: a lithography mask having a plurality of patterns, whereinat least one of the plurality of patterns is shaped as a parallelogramin a top view.
 2. The semiconductor fabrication apparatus of claim 1,wherein the at least one of the plurality of patterns shaped as theparallelogram in the top view is a first pattern, and wherein theplurality of patterns comprises a second pattern that is shaped as arectangle in the top view.
 3. The semiconductor fabrication apparatus ofclaim 2, wherein the lithography mask is configured to be positionedover a projection optics apparatus that has an aperture, and wherein alocation of the second pattern is aligned with a center of the aperture.4. The semiconductor fabrication apparatus of claim 3, wherein theaperture is shaped as a portion of an arc.
 5. The semiconductorfabrication apparatus of claim 2, wherein the first pattern and thesecond pattern are associated with different azimuthal angles.
 6. Thesemiconductor fabrication apparatus of claim 2, wherein the plurality ofpatterns comprises a third pattern that is shaped as a differentparallelogram in the top view, and wherein the first pattern and thethird pattern point in different directions.
 7. The semiconductorfabrication apparatus of claim 6, wherein the second pattern is locatedbetween the first pattern and the third pattern.
 8. The semiconductorfabrication apparatus of claim 2, wherein the first pattern and thesecond pattern each correspond to a gate line pattern of a transistor.9. The semiconductor fabrication apparatus of claim 1, wherein thelithography mask is an extreme ultraviolet (EUV) lithography mask.
 10. Asemiconductor lithography system, comprising: a projection opticsapparatus configured to transfer layout patterns of an extremeultraviolet (EUV) lithography mask onto a wafer, wherein the projectionoptics apparatus includes an aperture through which radiation passes;and the EUV lithography mask, wherein the EUV lithography mask containsa plurality of patterns, wherein at least one of the plurality ofpatterns is shaped as a parallelogram in a top view.
 11. Thesemiconductor lithography system of claim 10, wherein the at least oneof the plurality of patterns shaped as the parallelogram in the top viewis a first pattern, and wherein the plurality of patterns comprises asecond pattern that is shaped as a rectangle in the top view.
 12. Thesemiconductor lithography system of claim 11, wherein a location of thesecond pattern corresponds with a center of the aperture, and whereinthe aperture is curved.
 13. The semiconductor lithography system ofclaim 11, wherein the plurality of patterns comprises a third patternthat is shaped as a different parallelogram in the top view, and whereinthe first pattern and the third pattern point in different directions.14. The semiconductor lithography system of claim 13, wherein the secondpattern is located between the first pattern and the third pattern. 15.The semiconductor lithography system of claim 13, wherein the first,second, and third patterns are associated with different azimuthalangles that are functions of locations of the first, second, and thirdpatterns, respectively.
 16. The semiconductor lithography system ofclaim 13, wherein the first, second, and third patterns each correspondto respective a gate line pattern of a transistor.
 17. A method,comprising: generating a layout for a lithography mask based on a designlayout of a semiconductor device, wherein the generating comprisesadjusting orientations of one or more layout patterns of the designlayout such that a first pattern of a plurality of patterns is shaped asa parallelogram in a top view.
 18. The method of claim 17, wherein asecond pattern of the plurality of patterns is shaped as a rectangle inthe top view without being adjusted, and wherein the first pattern andthe second pattern define gate lines of a transistor.
 19. The method ofclaim 18, further comprising: placing a projection optics apparatusunder the lithography mask, the projection optics apparatus having acurved slit whose center is aligned with the second pattern.
 20. Themethod of claim 17, further comprising: performing an extremeultraviolet (EUV) lithography process using the lithography mask.